Integrated circuit having at least two vertical MOS transistors and method for manufacturing same,申请号US20020081902-传众专利搜索

Integrated circuit having at least two vertical MOS transistors and method for manufacturing same

申请公布号：US2002094628(A1)

申请号：US20020081902

申请日期：2002.02.22

申请公布日期：2002.07.18

申请人：

GOEBEL BERND;BERTAGNOLLI EMMERICH

发明人：GOEBEL BERND;BERTAGNOLLI EMMERICH

分类号：H01L21/8238;H01L27/092;(IPC1-7):H01L21/823;H01L21/336

主分类号：H01L21/8238

摘要：An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent at a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.