METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE,申请号US201615091700-传众专利搜索

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

申请公布号：US2016218191(A1)

申请号：US201615091700

申请日期：2016.04.06

申请公布日期：2016.07.28

申请人：

Unisantis Electronics Singapore Pte. Ltd.

发明人：MASUOKA Fujio;NAKAMURA Hiroki

分类号：H01L29/423;H01L21/28;H01L29/66;H01L27/115

主分类号：H01L29/423

地址：Peninsula Plaza SG

摘要：A method of fabricating a semiconductor device includes forming fin-shaped semiconductor layers on a semiconductor substrate. First and second pillar-shaped semiconductor layers are formed, and first and second control gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second selection gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second contact electrodes are formed around upper portions of the first and second pillar-shaped semiconductor layers, respectively.

主权项：1. A method for manufacturing a semiconductor device, the method comprising: a first step that includes: forming fin-shaped semiconductor layers on a semiconductor substrate, andforming a first insulating film around the fin-shaped semiconductor layers; a second step following the first step, the second step including forming second insulating films around the fin-shaped semiconductor layers,depositing a first polysilicon planarization layer on the second insulating films,forming a resist, andetching the first polysilicon planarization layer, the second insulating film, and the fin-shaped semiconductor layers to form first pillar-shaped semiconductor layers, a first dummy gate, second pillar-shaped semiconductor layers, and a second dummy gate; a third step following the second step, the third step including forming a third insulating film around the first pillar-shaped semiconductor layers, the second pillar-shaped semiconductor layers, the first dummy gate, and the second dummy gate,depositing a second polysilicon around the third insulating film, andetching the second polysilicon so that the second polysilicon remains on side walls of the first dummy gate, the first pillar-shaped semiconductor layers, the second dummy gate, and the second pillar-shaped semiconductor layers to form a third dummy gate and a fourth dummy gate; a fourth step including forming first diffusion layers in upper portions of the fin-shaped semiconductor layers, andforming a fourth insulating film around the third dummy gate and the fourth dummy gate; a fifth step following the fourth step, the fifth step including depositing a first interlayer insulating planarization film, and planarizing the first interlayer insulating planarization film exposing upper portions of the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate,removing the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate, andremoving the second insulating films and the fourth insulating film; a sixth step following the fifth step, the sixth step including forming a fifth insulating film,depositing a gate conductive film,etching back the gate conductive film to form a first control gate around the first pillar-shaped semiconductor layers and a second control gate around the second pillar-shaped semiconductor layers, andremoving exposed portions of the fifth insulating film to form a first gate insulating film and a second gate insulating film and including a charge storing layer around the first pillar-shaped semiconductor layers, around the second pillar-shaped semiconductor layers, and on inner surfaces of the fourth insulating film; a seventh step following the sixth step, the seventh step including depositing a sixth insulating film to form a third gate insulating film and a fourth gate insulating film, around the first pillar-shaped semiconductor layers, on the first control gate, around the second pillar-shaped semiconductor layers, and on the second control gate,depositing a gate conductor, andetching back the gate conductor to form a first selection gate around the first pillar-shaped semiconductor layers and a second selection gate around the second pillar-shaped semiconductor layers; and an eighth step following the seventh step, the eighth step including depositing a seventh insulating film to form a fifth gate insulating film and a sixth gate insulating film, around the first pillar-shaped semiconductor layers, on the first selection gate, around the second pillar-shaped semiconductor layers, and on the second selection gate,depositing a gate conductor, andetching back the gate conductor to form first contact electrodes around upper portions of the first pillar-shaped semiconductor layers and second contact electrodes around upper portions of the second pillar-shaped semiconductor layers.