Method for manufacturing semiconductor device,申请号US201514696007-传众专利搜索

Method for manufacturing semiconductor device

申请公布号：US9299770(B2)

申请号：US201514696007

申请日期：2015.04.24

申请公布日期：2016.03.29

申请人：

SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人：Koyama Masatoshi;Matsuura Kazuaki;Komatani Tsutomu

分类号：H01L21/302;H01L29/06;H01L29/66;H01L21/02;H01L29/778;H01L21/311;H01L29/20;H01L29/417

主分类号：H01L21/302

代理机构：

Westerman, Hattori, Daniels & Adrian, LLP

代理人：Westerman, Hattori, Daniels & Adrian, LLP

地址：Yokohama-shi JP

摘要：A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.

主权项：1. A method for manufacturing a semiconductor device comprising: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region; wherein the second active region is formed along the first active region, the third active region is formed directly in the inactive region so as to directly connect the first active region to the second active region, in a semiconductor layer; wherein forming the inactive region includes a step of forming a resist pattern on the semiconductor layer, the resist pattern having a first region covering the first active region, a second region covering the second active region and a third region covering the third active region, the third region of the resist pattern connects directly the first region to the second region of the resist pattern, the third region having width smaller than that of the first and second regions and a step of implanting ions to the other region of the semiconductor layer that is exposed out of the resist pattern; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching.