METHOD OF CREATING A MASKLESS AIR GAP IN BACK END INTERCONNECTIONS WITH DOUBLE SELF-ALIGNED VIAS,申请号US201514630572-传众专利搜索

METHOD OF CREATING A MASKLESS AIR GAP IN BACK END INTERCONNECTIONS WITH DOUBLE SELF-ALIGNED VIAS

申请公布号：US2015171012(A1)

申请号：US201514630572

申请日期：2015.02.24

申请公布日期：2015.06.18

申请人：

INTEL CORPORATION

发明人：CHANDHOK Manish;YOO Hui Jae;BORODOVSKY Yan A.;GSTREIN Florian;SHYKIND David N.;LIN Kevin L.

分类号：H01L23/522;H01L21/3213;H01L21/768;H01L23/528;H01L23/532

主分类号：H01L23/522

地址：Santa Clara CA US

摘要：A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

主权项：1. A method comprising: patterning an interconnect material on a integrated circuit substrate; patterning a thickness dimension of the interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line; and introducing a dielectric material on the interconnect material such that an end of the one or more vias are exposed through the dielectric material.