SRAM cells with dummy insertions
申请公布号:US9053974(B2)
申请号:US201213594620
申请日期:2012.08.24
申请公布日期:2015.06.09
发明人:Chen Chao-Hsuing;Wang Ling-Sung;Lin Chi-Yen
分类号:H01L21/70;H01L27/11;H01L27/02
主分类号:H01L21/70
代理人:Slater & Matsil, L.L.P.
地址:Hsin-Chu TW
摘要:A device includes a first pull-up transistor, a second pull-up transistor, and a dummy gate electrode between the first and the second pull-up transistors. The first and the second pull-up transistors are included in a first Static Random Access Memory (SRAM) cell.
主权项:1. A device comprising: a first pull-up transistor; a second pull-up transistor; and a dummy gate electrode between the first and the second pull-up transistors, wherein the first and the second pull-up transistors are comprised in a first Static Random Access Memory (SRAM) cell.
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