Sensing memory element logic states from bit line discharge rate that varies with resistance,申请号US201213570305-传众专利搜索

Sensing memory element logic states from bit line discharge rate that varies with resistance

申请公布号：US8848419(B2)

申请号：US201213570305

申请日期：2012.08.09

申请公布日期：2014.09.30

申请人：

Taiwan Semiconductor Manufacturing Co., Ltd.

发明人：Wu Jui-Jen;Chang Meng-Fan

分类号：G11C11/00

主分类号：G11C11/00

代理机构：

Duane Morris LLP

代理人：Duane Morris LLP

地址：Hsin-Chu TW

摘要：A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

主权项：1. An integrated circuit memory, comprising: a bit cell storing a logical bit value in a state of a memory element that has a changeable resistance, the memory element being coupled to a bit line at least when the bit cell is addressed during a read operation; a sense circuit coupled to the bit line for reading the logical bit value from the bit cell during the read operation, wherein addressing the bit cell couples said changeable resistance of the memory element onto the bit line; wherein the sense circuit comprises a sense circuit latch, and two level detectors that are switchable for controlling a logic state of the sense circuit latch; wherein one of the level detectors of the sense circuit is coupled to the bit line and another of the level detectors is coupled to a reference bit line providing a resistance that is greater and less than the changeable resistance and a changeable current amplitude when the bit cell is storing different said logical bit values; wherein level coupled to the level detectors by the respective bit line and reference bit line ramp to a switching threshold of the level detectors at rates that differ with the changeable resistance of the memory element of the bit cell; and, wherein the logic state of the sense circuit latch is set by the first of the bit line and the reference bit line to meet the switching threshold.