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Burst mode receiver and receiving method for generating on-chip reset signal

申请公布号:KR100948829(B1)

申请号:KR20070091149

申请日期:2007.09.07

申请公布日期:2010.03.22

分类号:H04B10/61;H04B10/25

主分类号:H04B10/61

摘要:A burst mode receiver for generating a on-chip reset signal and a burst mode receiving method are provided to generate the on-chip reset signal without a separate apparatus such as a bottom-hold circuit to obtain a quick response without supplying the reset signal to the outside, thereby applying the on-chip reset signal to an EPON(Ethernet Passive Optical Network) ideally. A burst mode receiver includes a burst mode receiving unit and a control unit. The burst mode receiving unit comprises a photo detector(10), a dummy TIA(Trans Impedance Amplifier)(12), a single-to-differential converter(13), a differential amplifier(14). The control unit comprises an AGC(Auto Gain Control) control unit(15), first and second LPFs(Low Pass Filters)(16,17), a differential quantizer(18), a logic control unit(19). The photo detector converts an input optical signal into a current signal. The core TIA amplifies a current outputted in a photo diode and converts the amplified current into a voltage. The single-to-differential converter compares a single terminal output voltage outputted by a core TIA(11) with a bias voltage generated by the dummy TIA to convert signal terminal output into differential output of which the phase is contrary to that of the bias voltage from the dummy TIA. The differential amplifier provides the amplification and output impedance matching of the differential output of the signal-to-differential converter and performs offset correction as necessary. The AGC control unit detects the voltage of the output terminal of the single-to-differential converter and outputs a digital control signal for AGC. The LPFs output substantial DC(Direct Current) values for the voltage swings of node 3 and node 4. The differential quantizer quantizes a difference between voltage outputted from the LPFs and outputs the difference as a digital value, and outputs a reset_enable signal in the falling edge of a burst signal with high power. The logic control unit generates an AGC signal from the output of the AGC control unit and outputs the AGC signal to the core TIA to control the gain of the core TIA.

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