Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features,申请号US20030348093-传众专利搜索

Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features

申请公布号：US6794691(B2)

申请号：US20030348093

申请日期：2003.01.21

申请公布日期：2004.09.21

申请人：

AMI SEMICONDUCTOR, INC.

发明人：NELSON MARK MICHAEL

分类号：H01L21/3105;H01L23/528;H01L23/544;(IPC1-7):H01L29/73

主分类号：H01L21/3105

摘要：A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduced capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.