ADRESSENERZEUGUNG UND DATENPFADARBITRIERUNG FÜR SRAM ZUR ANPASSUNG VON MEHREREN ÜBERTRAGENEN PAKETEN,申请号DE1997606443-传众专利搜索

ADRESSENERZEUGUNG UND DATENPFADARBITRIERUNG FÜR SRAM ZUR ANPASSUNG VON MEHREREN ÜBERTRAGENEN PAKETEN

申请公布号：DE69706443(D1)

申请号：DE1997606443

申请日期：1997.02.04

申请公布日期：2001.10.04

申请人：

ADVANCED MICRO DEVICES, INC.

发明人：SINGH, ALOK;ROY, RAJAT;KUO, JERRY

分类号：G06F13/12;(IPC1-7):G06F13/12

主分类号：G06F13/12

摘要：An ethernet controller for controlling the transmission of data between a station and an ethernet having four FIFOs for managing the transmission of data between the station CPU, a memory buffer, and the ethernet. The four FIFOs each have a selected size to maximize performance of the controller. The controller includes a arbiter to arbitrate which pending requests from each of the FIFOs will have priority. The controller limits the transmission of data by each FIFO to 32 bytes per grant. Each FIFO includes logic to convert data in a first bit size format to a second bit size format. The controller also includes logic to convert a 16 bit address to two 8 bit portions for transmission over an 8 bit address bus and logic to reformat the two 8 bit portions to the 16 bit address.