METHOD FOR BOTTOMLESS DEPOSITION OF BARRIER LAYERS IN INTEGRATED CIRCUIT METALLIZATION SCHEMES,申请号US2000023252-传众专利搜索

METHOD FOR BOTTOMLESS DEPOSITION OF BARRIER LAYERS IN INTEGRATED CIRCUIT METALLIZATION SCHEMES

申请公布号：WO2001015220(A1)

申请号：US2000023252

申请日期：2000.08.24

申请公布日期：2001.03.01

摘要：<p>Methods are disclosed for selective deposition on desired materials. In particular, barrier materials are selectively formed on insulating surfaces, as compared to conductive surfaces. In the context of contact formation and trench fill, particularly damascene and dual damascene metallization, the method advantageously lines insulating surfaces (12, 13) with a barrier material (26). The selective formation allows the deposition to be 'bottomless', thus leaving the conductive material (20) at a via bottom (10) exposed for direct metal-to-metal contact when further conductive material (18) is deposited into the opening (22) after barrier formation on the insulating surfaces (12, 13). Desirably, the selective deposition is accomplished by atomic layer deposition (ALD), resulting in highly conformal coverage of the insulating sidewalls (12, 13) in the opening.</p>