Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure,申请号US19990252470-传众专利搜索

Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure

申请公布号：US6177340(B1)

申请号：US19990252470

申请日期：1999.02.18

申请公布日期：2001.01.23

申请人：

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

发明人：YOO CHUE-SAN;WANG CHEN JONG;CHIANG WEN CHUAN

分类号：H01L21/311;H01L21/768;H01L21/8242;H01L27/108;(IPC1-7):H01L21/476

主分类号：H01L21/311

摘要：A method for reducing the high aspect ratios, encountered when forming, and filling, narrow diameter contact holes, in thick insulator layers, has been developed, featuring a two step contact hole opening and filling procedure. First, lower narrow diameter contact holes are opened in lower levels of insulator layers, then filled with tungsten. After deposition of upper levels of insulator layers, upper narrow diameter contact holes are formed, exposing the tungsten filled, lower diameter contact holes. A second tungsten layer fills the upper, narrow diameter contact hole, resulting in a final narrow diameter contact hole, in thick insulator layers, formed with reduced aspect ratios, via use of the two contact hole openings, and the two tungsten fill procedures. In addition these procedures allow a damascene, tungsten bit line structure, to be formed in a dual shaped opening, in lower insulator layers.