Via alignment, etch completion, and critical dimension measurement method and structure,申请号US19980167655-传众专利搜索

Via alignment, etch completion, and critical dimension measurement method and structure

申请公布号：US6162650(A)

申请号：US19980167655

申请日期：1998.10.05

申请公布日期：2000.12.19

申请人：

VLSI TECHNOLOGY, INC.

发明人：HARVEY, IAN ROBERT;SETHI, SATYENDRA

分类号：H01L23/544;(IPC1-7):H01L21/00

主分类号：H01L23/544

摘要：A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.