Variable period and assertion width REQ/ACK pulse generator for synchronous SCSI data transfers,申请号US19970796707-传众专利搜索

Variable period and assertion width REQ/ACK pulse generator for synchronous SCSI data transfers

申请公布号：US5862352(A)

申请号：US19970796707

申请日期：1997.02.06

申请公布日期：1999.01.19

申请人：

LSI LOGIC CORPORATION

发明人：MURESAN, MATTHEW C.

分类号：G06F13/42;(IPC1-7):G06F13/14

主分类号：G06F13/42

摘要：A circuit for embedding within a SCSI control device for generating REQ or ACK signals in a flexible manner as required for SCSI synchronous data transfer mode. The circuit of the present invention utilizes a single counter and associated logic to provide flexible waveform generation of the REQ or ACK signal in a SCSI control device. The counter value counts up from zero and is compared against one of two values applied to a comparator. The first value is the desired period (duration) of the assertion of the REQ/ACK signal. When this count value is reached, the counter is restarted, the REQ/ACK signal is de-asserted, and the second count value-the de-assertion time-is applied to the comparator. When the second count is reached, the cycle starts over. An enable and reset signal allow other portions of the SCSI control device to start, stop, and reset the counter circuit of the present invention as required for SCSI synchronous data transfer controls. An alternative embodiment of the invention utilizes a down counter circuit which may embed a comparison against zero thereby obviating the need for a separate comparator circuit. The waveform generated may be applied to either the REQ signal in a target mode of the SCSI device or to the ACK signal in the initiator mode of the SCSI device.