CLOCK SWITCHING CIRCUIT

申请公布号：JPH0998161(A)

申请号：JP19950253329

申请日期：1995.09.29

申请公布日期：1997.04.08

申请人：

OKI ELECTRIC IND CO LTD

发明人：ATSUKAWA HITOSHI;ONODA KOICHI;ITO TOSHIYUKI

分类号：H04L1/22;G06F1/06;H04L7/02

主分类号：H04L1/22

摘要：PROBLEM TO BE SOLVED: To prevent a glitch or a phase skip from being generated when selecting any one clock by switching the clocks of two systems. SOLUTION: A phase discrimination part 20 outputs phase information S20 from the phase difference of clocks A and B. When the phase information S20 is 'H', for example, a multiplexer 31 selects the clock B and inputs it to a multiplexer 33. A switching timing preparation part 10 outputs a switching timing signal S10 to the multiplexer 33. When a switch signal sel of 'H' is latched by a D-FF 12 by the fall of an output signal S11, the switching timing signal S10 becomes 'H'. Then, the multiplexer 33 outputs the clock B, which is an output signal 531 of the multiplexer 31, as a clock C. Therefore, no glitch is generated in the clock C and the phase skip more than ±90 deg. does not occur.

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