NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
申请公布号:JPH0447596(A)
申请号:JP19900158362
申请日期:1990.06.15
申请公布日期:1992.02.17
发明人:TERADA YASUSHI;NAKAYAMA TAKESHI;HAYASHIGOE MASANORI;MIYAWAKI YOSHIKAZU;KOBAYASHI SHINICHI
分类号:G11C17/00;G11C16/02;G11C16/04;G11C16/06;H01L21/8247;H01L27/10;H01L27/115
主分类号:G11C17/00
摘要:PURPOSE:To reduce the danger of over deletion by applying high pressure applied from the outside at the time of data deletion to the source of a memory transistor and also applying the same degree of high pressure to a drain. CONSTITUTION:A bit line high pressure switch 400 is provided between a memory array 1 and a source line switch 150, and a boosting circuit 500 is provided between the bit line high pressure switch 400 and a switch circuit 600. High pressure Vpp outputted from the switch circuit 600 at the time of data deletion is applied not only to the source line switch 150 but also to the boosting circuit 500. Therefore, since the high pressure is applied not only to a source 230 but also to a drain 220 at the time of data deletion, the electric potential of a floating gate 210 becomes higher than the conventional one. Thus, the strength of an electric field over between the floating gate and the secure 230 is alleviated so that the energy consumption at the time of data deletion can be reduced and the danger of over deletion can be reduced.
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