RESET CIRCUIT FOR LOGICAL CIRCUIT,申请号JP19890253381-传众专利搜索

RESET CIRCUIT FOR LOGICAL CIRCUIT

申请公布号：JPH03113616(A)

申请号：JP19890253381

申请日期：1989.09.28

申请公布日期：1991.05.15

申请人：

KOUFU NIPPON DENKI KK

发明人：ISHIKURA HIROSHI

分类号：G06F1/24

主分类号：G06F1/24

摘要：<p>PURPOSE:To improve reliability and operability of a machine by outputting a reset signal to a logic circuit when the coincidence of a state value showing the operation state of the logic circuit with a prescribed value which is previous ly set is detected. CONSTITUTION:The logic circuit 1 regularly operates while it expresses the operation state and a state where nothing is operated as the state values 101. If the initial state value 101 comes to '10' when power is supplied to the logical circuit 1, a comparison circuit 3 detects coincidence because the state value 101 from the logic circuit 1 and a state value 102 from a state table 2 are both '10' and sets a request signal 103 from a pulse generation circuit 4 to be effective. When a request signal 103 from the comparison circuit 3 comes to be effective, the pulse generation circuit 4 generates the reset pulse signal of the logic circuit 1 and outputs the pulse signal to the logical circuit 1 as a reset signal 104. Thus, an initial state value can be set constant by preparing a reset-only processing and without executing it, and reliability and operability of the machine can be improved.</p>