INTERMITTENT RECEIVER CONTROLLER
申请公布号:JPH09113654(A)
申请号:JP19950266939
申请日期:1995.10.16
申请公布日期:1997.05.02
发明人:MASUDA KAZUAKI
分类号:G04G3/00;G04G3/02;G04G5/00;G04G7/02;G06F1/04;G06F1/08;G06F1/14;H04B7/26
主分类号:G04G3/00
摘要:<p>PROBLEM TO BE SOLVED: To shorten a continuous reception functioning time functioned with a reference clock and reduce power consumption by calculating a set count value corresponding to an intermittent receiving period in response to the comparison signal between the reference clock and a time clock and counting with the time clock to this set value. SOLUTION: A counter measurement value calculation circuit 5 calculates a counter setting value N in response to the comparison result H between a reference clock CR supplied from a frequency comparison circuit 4 and a time clock CK and supplies it to a counter 3. The counter 3 counts the clock CK to this set value N and outputs the count value to an output terminal TP as an intermittent receiving period P. In this manner, the measuring time of the period P is set with the period step of the clock CK and so the maximum error of the measuring time is within 1/2 period of the clock CK. Also, as the intermittent reception period measuring error is small, the continuous reception operation time operated with the clock CR can be shortened by performing the intermittent period measurement of long term to the degree so as not to be out of phase in intermittent reception.</p>
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