Phase control circuit for controlling phase of video signal and sampling clock signal,申请号US19930108610-传众专利搜索

Phase control circuit for controlling phase of video signal and sampling clock signal

申请公布号：US5396295(A)

申请号：US19930108610

申请日期：1993.08.31

申请公布日期：1995.03.07

申请人：

FANUC LTD.

发明人：FURUTA, SATOSHI

分类号：G09G3/20;G09G5/12;H04N3/12;H04N5/66;(IPC1-7):H04N5/04

主分类号：G09G3/20

摘要：PCT No. PCT/JP93/00033 Sec. 371 Date Aug. 31, 1993 Sec. 102(e) Date Aug. 31, 1993 PCT Filed Jan. 12, 1993 PCT Pub. No. WO93/15498 PCT Pub. Date Aug. 5, 1993.A phase control circuit, which can be operated easily, automatically controls the phase of a video signal and a sampling clock signal. A delay circuit (24) outputs delayed clock pulses (DP) that are out of phase with each other, and switching circuits (25a DIFFERENCE 25c) select one, at a time, of the delayed clock pulses (DP) that are out of phase with each other in response to respective switching signals (SS1 DIFFERENCE SS3) from a control circuit (23), Counters (28a DIFFERENCE 28c) count pixel data (ED) latched by data latch circuits (26a DIFFERENCE 26c) each time the delayed clock pulses (DP) are outputted by the corresponding switching circuits (25a DIFFERENCE 25c), The control circuit (23) confirms the counts of the counters in each frame period, and controls a switching circuit (25d) to select a clock pulse in phase with the delayed clock pulse (DP) from the switching circuit (25b) and output the selected clock pulse to a panel display unit all the counts are equal to or greater than the count of the counter (28b) first sampling screen pattern.