Testing circuit provided in digital logic circuits,申请号US19920937653-传众专利搜索

Testing circuit provided in digital logic circuits

申请公布号：US5392296(A)

申请号：US19920937653

申请日期：1992.08.31

申请公布日期：1995.02.21

申请人：

NEC CORPORATION

发明人：SUZUKI, HIROAKI

分类号：G01R31/28;G01R31/3185;G06F11/22;G11C29/00;G11C29/56;H03K19/00;(IPC1-7):G01R31/28

主分类号：G01R31/28

摘要：A testing circuit for scan-pass testing an integrated circuit comprises a chain of serially connected scan-pass registers where an individual scan-pass register in the chain can be programmably selected for observation at a shift-out port located at the last scan-pass register in the serial chain. To programmably select a particular register, while a test signal is held active, a clock is pulsed and each clock pulse selects the next scan-pass register in the chain for observation, starting with the first scan-pass register. The register selected when the test signal becomes inactive is the register that is observed at the shift-out port at the end of the scan-pass register chain. The testing circuit permits the value of any register in the chain to be output in real-time without circuit interruption.