Process for forming lightly-doped-grain (LDD) structure in integrated circuits.,申请号EP19860307280-传众专利搜索

Process for forming lightly-doped-grain (LDD) structure in integrated circuits.

申请公布号：EP0218408(A2)

申请号：EP19860307280

申请日期：1986.09.22

申请公布日期：1987.04.15

申请人：

HEWLETT-PACKARD COMPANY

发明人：CHIU, KUANG YI;HSU, FU CHIEH

分类号：H01L21/033;H01L21/265;H01L21/336;H01L21/8238;H01L29/78;(IPC1-7):H01L21/00;H01L21/28;H01L29/08

主分类号：H01L21/033

摘要：<p>A new lightly doped drain (LDD) process which does not require extra masking steps as compared to the conventional CMOS process employs a two layer side wall spacer technology, in which the LDD ion implantation for n-channel and p-channel devices can be carried out by sharing the n<+> or p<+> source and drain ion implantation mask. This provides maximum flexibility in designing optimum n- and p-channel LDD MOSFETs without using any additional mask steps other than the conventional CMOS mask levels, and is also compatible with self-aligned silicide process.</p>