SEMICONDUCTOR INTEGRATED CIRCUIT, AND DESIGN SYSTEM THEREFOR,申请号JP20060065503-传众专利搜索

SEMICONDUCTOR INTEGRATED CIRCUIT, AND DESIGN SYSTEM THEREFOR

申请公布号：JP2007240414(A)

申请号：JP20060065503

申请日期：2006.03.10

申请公布日期：2007.09.20

申请人：

TOSHIBA CORP

发明人：YASUKURA KENICHI;TOKUNAGA CHIKAKO;HASEGAWA SATORU

分类号：G01R31/28;H01L21/822;H01L27/04

主分类号：G01R31/28

摘要：<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing an electric power consumption during a test, without adding a clock switching circuit to a clock route, and also to provide a design system therefor. <P>SOLUTION: This semiconductor integrated circuit is provided with: a pattern generator for generating a pattern for executing a BIST (Built-In Self Test) of a logic circuit; a pattern compressor for compressing a data output from the logic circuit to output; a logic BIST circuit having a logic BIST control part for controlling the pattern generator and the pattern compressor, and for controlling an operation of shifting the pattern by a scan path of the logic circuit; a memory; and a memory BIST circuit for executing the BIST in the memory. The logic BIST circuit is set to a low electric power consumption mode during the memory BIST circuit executes the BIST in the memory; the pattern generator maintains a holding condition of the data just before the logic BIST circuit is brought into the low electric power consumption mode, and generates a fixed value in stead of the pattern to input into the logic circuit, and the pattern compressor keeps the holding condition of the data just before the logic BIST circuit is brought into the low electric power consumption mode, and stops a compression operation. <P>COPYRIGHT: (C)2007,JPO&INPIT