GATE DRIVING CIRCUIT OF HIGH-SIDE TRANSISTOR, SWITCHING OUTPUT CIRCUIT, INVERTER DEVICE, AND ELECTRONIC DEVICE,申请号US201514833389-传众专利搜索

GATE DRIVING CIRCUIT OF HIGH-SIDE TRANSISTOR, SWITCHING OUTPUT CIRCUIT, INVERTER DEVICE, AND ELECTRONIC DEVICE

申请公布号：US2016065205(A1)

申请号：US201514833389

申请日期：2015.08.24

申请公布日期：2016.03.03

申请人：

ROHM CO., LTD.

发明人：NIIKURA Hiroki;MORINAKA Takafumi

分类号：H03K17/687;H02P27/06;H02M7/5387

主分类号：H03K17/687

地址：UKYO-KU JP

摘要：A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse.

主权项：1. A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted, and turning off the high-side transistor when an input reset pulse is asserted, comprising: a level shift circuit configured to level-shift each of an input set pulse and an input reset pulse to generate an intermediate set pulse and an intermediate reset pulse; a first inverter having a first threshold value, and configured to receive the intermediate set pulse to generate a first set pulse; a second inverter having a second threshold value different from the first threshold value, and configured to receive the intermediate set pulse to generate a second set pulse; a third inverter having the first threshold value, and configured to receive the intermediate reset pulse to generate a first reset pulse; a fourth inverter having the second threshold value, and configured to receive the intermediate reset pulse to generate a second reset pulse; a logic circuit configured to mask the first set pulse by using the second reset pulse to generate an output set pulse, and mask the first reset pulse by using the second set pulse to generate an output reset pulse; a flip-flop configured to receive the output set pulse and the output reset pulse to thereby output a driving pulse of which a level transitions; and a driver configured to drive a high-side transistor according to the driving pulse.