DICING METHOD FOR WAFER-LEVEL PACKAGING AND SEMICONDUCTOR CHIP WITH DICING STRUCTURE ADAPTED FOR WAFER-LEVEL PACKAGING,申请号WO2015EP61302-传众专利搜索

DICING METHOD FOR WAFER-LEVEL PACKAGING AND SEMICONDUCTOR CHIP WITH DICING STRUCTURE ADAPTED FOR WAFER-LEVEL PACKAGING

申请公布号：WO2015181050(A1)

申请号：WO2015EP61302

申请日期：2015.05.21

申请公布日期：2015.12.03

申请人：

AMS AG

发明人：STERING, BERNHARD

分类号：H01L21/78;H01L21/56;H01L23/31

主分类号：H01L21/78

摘要：A semiconductor substrate (1) is provided with integrated circuits. Dicing trenches (7) are formed in the substrate (1) between the integrated circuits, a polyimide layer (8) spanning the trenches (7) is applied above the integrated circuits, a tape layer (14) is applied above the polyimide layer (8), and a layer portion of the substrate (1) is removed from the substrate side (17) opposite the tape layer (14), until the trenches (7) are opened and dicing of the substrate (1) is thus effected. The polyimide layer (8) is severed in sections (18) above the trenches (7) when the tape layer (14) is removed. The semiconductor chip is provided with a cover layer (11) laterally confining the polyimide layer (8) near the trenches (7), in particular for forming breaking delimitations (9).