Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures,申请号US201213490931-传众专利搜索

Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures

申请公布号：US8856546(B2)

申请号：US201213490931

申请日期：2012.06.07

申请公布日期：2014.10.07

申请人：

Intel Corporation

发明人：Gueron Shay;Krasnov Vlad

分类号：G06F21/00;H04L9/28

主分类号：G06F21/00

代理机构：

Kenyon & Kenyon LLP

代理人：Kenyon & Kenyon LLP

地址：Santa Clara CA US

摘要：A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm.

主权项：1. A processor comprising: a controller to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks; logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks; and circuits to generate a message digest conforming to the selected SHA algorithm, wherein each of the message schedules is designated for use in the compression for one of the plurality of message blocks, each of the message schedules is derived based upon more than one of the plurality of the message blocks, and more than one of the plurality of the message blocks are processed using single instruction multiple data (SIMD) instructions in each of a plurality of loop iterations to derive respective ones of the message schedules.