SKEW ADJUSTMENT CIRCUIT, AND OPTICAL DISK DRIVE,申请号JP20120240531-传众专利搜索

SKEW ADJUSTMENT CIRCUIT, AND OPTICAL DISK DRIVE

申请公布号：JP2014089664(A)

申请号：JP20120240531

申请日期：2012.10.31

申请公布日期：2014.05.15

申请人：

RENESAS ELECTRONICS CORP

发明人：KATO TAKAHIRO

分类号：G06F1/06;G11B20/10;G11B20/14

主分类号：G06F1/06

摘要：<p>PROBLEM TO BE SOLVED: To make a skew adjustment of a polyphase clock signal which is applicable to high-speed recording of an optical disk drive.SOLUTION: A skew adjustment circuit is provided with a first delay circuit (303) for delaying a first clock signal; a second delay circuit (301) for delaying a second clock signal; and a third delay circuit (302) for delaying a third clock signal in an intermediate phase between the first clock signal and second clock signal. Further, the skew adjustment circuit is provided with a first logic gate (304) which exclusive ORs the output of the first delay circuit and the output of the third delay circuit, and a second logic gate (305) which exclusive ORs the output of the second delay circuit and the output of the third delay circuit. The skew adjustment circuit is provided with a feedback path (FBR) for supplying a feedback voltage for adjusting a delay time of the third delay circuit based upon the difference between the output of the first logic gate and the output of the second logic gate to the third delay circuit, and makes a skew adjustment of a polyphase clock signal.</p>