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METHOD AND APPARATUS OF ADDRESS BUS CODING/DECODING FOR LOW-POWER VERY LARGE SCALE INTEGRATION SYSTEM

申请公布号:KR101311617(B1)

申请号:KR20060020164

申请日期:2006.03.02

申请公布日期:2013.09.26

分类号:G06F13/38

主分类号:G06F13/38

摘要:A method and a device for coding/decoding an address bus in a low-power VLSI system are provided to reduce power consumption by realizing a bit change rate of a bus value lower than a half of total bit number of the bus value. A binary bus value storing part(310) stores the previous bus value. A multi-bit determiner(330) outputs bit information controlling bit inversion by receiving the current bus value, and comparing the bit numbers of '0' and '1'. A bit inverter(350) selectively inverts the current bus value based on the bit information. A vector operator(370) performs vector operation of the selectively inverted current bus value and the previous bus value. An output line adds the bit information controlling the bit inversion to the bit value through vector operation, and outputs the information to the corresponding to bus.

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