METHOD FOR GENERATING DELAY LIBRARY AND DELAY LIBRARY GENERATION DEVICE,申请号JP20110225611-传众专利搜索

METHOD FOR GENERATING DELAY LIBRARY AND DELAY LIBRARY GENERATION DEVICE

申请公布号：JP2013088841(A)

申请号：JP20110225611

申请日期：2011.10.13

申请公布日期：2013.05.13

申请人：

RENESAS ELECTRONICS CORP

发明人：NAHATA AKIOMI

分类号：G06F17/50

主分类号：G06F17/50

摘要：<P>PROBLEM TO BE SOLVED: To shorten a post-processing time for a processing result of a static timing analysis tool. <P>SOLUTION: A method for generating a delay library is a method for generating a delay library of a macro internally performing frequency division of an input clock signal and includes: a step of extracting a frequency division circuit for internally performing the frequency division of the input clock signal, on the basis of design information of the macro; a correction step of correcting the design information so that the extracted frequency division circuit is regarded as a part of a clock line in static timing analysis; and a generation step of generating a delay library using the corrected design information. <P>COPYRIGHT: (C)2013,JPO&INPIT