View data sharing for efficient multi-mode multi-corner timing analysis,申请号US201414502611-传众专利搜索

View data sharing for efficient multi-mode multi-corner timing analysis

申请公布号：US9384310(B1)

申请号：US201414502611

申请日期：2014.09.30

申请公布日期：2016.07.05

申请人：

CADENCE DESIGN SYSTEMS, INC.

发明人：Keller Igor;Chen Jijun;Yadav Pradeep

分类号：G06F17/50

主分类号：G06F17/50

代理机构：

Kenyon & Kenyon LLP

代理人：Kenyon & Kenyon LLP

地址：San Jose CA US

摘要：A system and method for performing multi-mode multi-corner (MMMC) analysis such that multiple views or conditions can be analyzed together to improve runtime by taking advantage of common steps of analysis in different corners. Views are clustered based on their similarity to one another to take advantage of calculations and other tasks that may be shared between views during timing analysis. Then, during timing analysis, each net in the design is analyzed for each view.

主权项：1. A method for testing the timing of an integrated circuit design comprising: on a computer device having a processor configured to implement a simulator to test timing for the design for a plurality of conditions for each net in the design: identifying at least one of RC corners, library files, aggressor net constraints, and aggressor timing windows of each of two or more conditions of the plurality of conditions;comparing the at least one of RC corners, library files, aggressor net constraints, and aggressor timing windows of the two or more conditions;grouping the two or more conditions into a cluster based on the comparison, wherein, for the cluster:loading, into the simulator, (i) RC parameters and (ii) one or more library files for the net;performing, with the simulator, an RC reduction according to one or more restrictions as required by the two or more conditions in the cluster;loading, into the simulator, a plurality of input slews; andcalculating, with the simulator, for at least one condition of the two or more conditions in the cluster, a timing delay and an output slew for the net based on the plurality of input slews, wherein a result of at least one calculation is stored in memory and at least one of the timing delay and the output slew of the stored result is used to represent at least one of a timing delay and an output slew of another condition of the two or more conditions in the cluster.