Method, system and computer program product for verifying address generation, interlocks and bypasses

申请公布号：US8165864(B2)

申请号：US20080028038

申请日期：2008.02.08

申请公布日期：2012.04.24

申请人：

MULLEN MICHAEL P.;RICH MARVIN J.;SCHAFER JAMES L.;INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人：MULLEN MICHAEL P.;RICH MARVIN J.;SCHAFER JAMES L.

分类号：G06G7/62;G06F7/38;G06F11/00;G06F17/50

主分类号：G06G7/62

摘要：Method, system and computer program product for verifying the address generation, address generation interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values from a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second set of general purpose register values on a bus.

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