Verification method with the implementation of well voltage pseudo diodes,申请号US20070962945-传众专利搜索

Verification method with the implementation of well voltage pseudo diodes

申请公布号：US7895554(B2)

申请号：US20070962945

申请日期：2007.12.21

申请公布日期：2011.02.22

申请人：

TEXAS INSTRUMENTS INCORPORATED

发明人：CHU WEN-HWA M.;BARUA SHAIBAL;SPRINGER LILY X.;HOMACK JAMES

分类号：G06F9/455

主分类号：G06F9/455

摘要：A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.