ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS,申请号WO2010US22886-传众专利搜索

ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS

申请公布号：WO2010096263(A3)

申请号：WO2010US22886

申请日期：2010.02.02

申请公布日期：2010.11.11

申请人：

RAMBUS INC.;LIN, QI;PENG, LIANG;HAMPEL, CRAIG E.;SHEFFLER, THOMAS J.;WOO, STEVEN C.;RYCHLIK, BOHUSLAV

发明人：LIN, QI;PENG, LIANG;HAMPEL, CRAIG E.;SHEFFLER, THOMAS J.;WOO, STEVEN C.;RYCHLIK, BOHUSLAV

分类号：G06F15/16;G06F12/08;G06F15/167;G06F15/173

主分类号：G06F15/16

摘要：A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.