SEMICONDUCTOR SUBSTRATE WIRING DESIGN SUPPORT DEVICE AND CONTROL METHOD THEREOF,申请号US20100748736-传众专利搜索

SEMICONDUCTOR SUBSTRATE WIRING DESIGN SUPPORT DEVICE AND CONTROL METHOD THEREOF

申请公布号：US2010251190(A1)

申请号：US20100748736

申请日期：2010.03.29

申请公布日期：2010.09.30

申请人：

FUJITSU LIMITED

发明人：NAKAGAWA KOICHI

分类号：G06F17/50

主分类号：G06F17/50

摘要：A semiconductor substrate wiring design support device includes a memory unit that stores logical connection information and a wiring unit that performs wiring based on the logical connection information and provides a single via between a first and a second wire layer when the wiring is a wire between the first and the second wire layer. An isolated-via-error detection unit detects the single via as an isolated-via-error when only the single via is provided in a case where a plurality of vias may be needed according to a via alteration rule. An isolated-via-error-treatment via alteration unit alters a single via detected as the isolated-via-error to an isolated-via-error-treatment via, and a redundancy via alteration unit alters a single via to a redundancy via after the alteration to the isolated-via-error-treatment via.