Dual-frequency matching circuit,申请号US20090352194-传众专利搜索

Dual-frequency matching circuit

申请公布号：US7639099(B2)

申请号：US20090352194

申请日期：2009.01.12

申请公布日期：2009.12.29

申请人：

PANASONIC CORPORATION

发明人：SANGAWA USHIO

分类号：H03H7/38

主分类号：H03H7/38

摘要：The connection topology of input terminals 2, elements 4a, 4b, 4c and 4d and load 5 is designed similarly to a so-called "seven-segment display", which is often used to display numerals on an electronic calculator or a digital watch. More specifically, suppose in the three horizontally running segments, the top and bottom segments are associated with the input terminals 2 and the load 5 is allocated to one of the four vertically running segments. Then, the three other vertical segments and the other horizontal segment are associated with the elements 4a, 4b, 4c and 4d, which are an inductor with an inductance of 5.119 nH, a capacitor with a capacitance of 1.370 pF, an inductor with an inductance of 8.360 nH and a capacitor with a capacitance of 5.942 pF, respectively. By adopting this circuit configuration, the total number of elements can be reduced to four and the loss can be reduced significantly. In addition, since the resonant circuits can be eliminated and the size of the ladder circuit can be reduced, impedance matching is achieved with a high degree of stability.