Frequency divider monitor of phase lock loop,申请号US20070765475-传众专利搜索

Frequency divider monitor of phase lock loop

申请公布号：US7627835(B2)

申请号：US20070765475

申请日期：2007.06.20

申请公布日期：2009.12.01

发明人：FENG KAI DI;JIN ZHENRONG

分类号：G06F17/50

主分类号：G06F17/50

摘要：A design structure for designing, manufacturing, and/or testing a frequency divider and monitoring circuit. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.