SELF-SYNCHRONOUS DUPLE D FLIP-FLOP WITH HIGH ACTIVE LEVEL OF CONTROL SIGNAL,申请号RU20070141585-传众专利搜索

SELF-SYNCHRONOUS DUPLE D FLIP-FLOP WITH HIGH ACTIVE LEVEL OF CONTROL SIGNAL

申请公布号：RU2365031(C1)

申请号：RU20070141585

申请日期：2007.11.12

申请公布日期：2009.08.20

申请人：

INSTITUT PROBLEM INFORMATIKI ROSSIJSKOJ AKADEMII NAUK (IPI RAN)

发明人：STEPCHENKOV JURIJ AFANAS'EVICH;D'JACHENKO JURIJ GEORGIEVICH;PLEKHANOV LEONID PETROVICH;GRINFEL'D FRUMA ISAAKOVNA;STEPCHENKOV DMITRIJ JUR'EVICH

分类号：H03K3/00

主分类号：H03K3/00

摘要：FIELD: physics; computer technology. ^ SUBSTANCE: invention concerns to pulse and computer technology and can use at construction of self-synchronous flip-flop, register and computing circuits, systems of digital information processing. This result is reached because the inverting element and four elements OR-AND-NOT are entered in the scheme containing two elements AND-OR-NOT, an information input, an operating input, direct and inverse information outputs and a display output are entered . ^ EFFECT: maintenance of self-synchronous realisation of the duple D flip-flop with high active level of a control signal, single-phase coding of an information input and paraphase coding of an information output. ^ 7 cl, 8 dwg