Wafer-level chip package process,申请号US20060464648-传众专利搜索

Wafer-level chip package process

申请公布号：US7541218(B2)

申请号：US20060464648

申请日期：2006.08.15

申请公布日期：2009.06.02

申请人：

ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人：HSU CHAIN-HAU

分类号：H01L21/00

主分类号：H01L21/00

摘要：A wafer-level chip package process is provided. First, a transparent substrate having a chip sealing layer and a transparent layer is provided. Then, the chip sealing layer is cut to form a first groove of a predetermined depth, and an adhesive is formed on the chip sealing layer. Next, a wafer having a back surface and an active surface is provided, and the transparent substrate is disposed on the active surface of the wafer, wherein the chip sealing layer is adhered to the active surface by the adhesive. Next, the transparent layer is cut to form a second groove corresponding to the first groove. Next, the back surface of the wafer is cut to form a third groove corresponding to the first groove. After that, the wafer and the transparent substrate are singulated to form a plurality of chip package structures.