ASYNCHRONOUS SEQUENCER CIRCUIT WITH FLEXIBLY ORDERED OUTPUT SIGNAL EDGES,申请号CA20022464890-传众专利搜索

ASYNCHRONOUS SEQUENCER CIRCUIT WITH FLEXIBLY ORDERED OUTPUT SIGNAL EDGES

申请公布号：CA2464890(C)

申请号：CA20022464890

申请日期：2002.10.25

申请公布日期：2008.09.30

申请人：

XILINX, INC.

发明人：NGUYEN, ANDY T.

分类号：H03K19/017;H03K19/173;G06F1/025;H03K5/13;H03K19/0175

主分类号：H03K19/017

摘要：An unlocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input termfinal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual- input latches that provide a set of sequencer output signals. The sequence o f the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed inp ut signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the outp ut signal is programmable, and the sequence of the trailing edges is independently programmable.