Layout structures in semiconductor memory devices including bit line layout for higher density migration
申请公布号:US7426129(B2)
申请号:US20050183613
申请日期:2005.07.18
申请公布日期:2008.09.16
发明人:CHOI BYUNG-GIL;SUH YOUNG-HO;KWAK CHOONG-KEUN
分类号:G11C5/06
主分类号:G11C5/06
摘要:A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.