DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE

申请公布号：US2008198700(A1)

申请号：US20080045059

申请日期：2008.03.10

申请公布日期：2008.08.21

申请人：

INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人：FRANCH ROBERT L.;HUOTT WILLIAM V.;JAMES NORMAN K.;RESTLE PHILLIP J.;SKERGAN TIMOTHY M.

分类号：G04F10/00;G01R31/317;G01R31/3185;G06F19/00

主分类号：G04F10/00

摘要：A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

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