SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DEVICE DESIGN SYSTEM, AND COMPUTER PROGRAM,申请号JP20070302106-传众专利搜索

SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DEVICE DESIGN SYSTEM, AND COMPUTER PROGRAM

申请公布号：JP2008171399(A)

申请号：JP20070302106

申请日期：2007.11.21

申请公布日期：2008.07.24

申请人：

ELPIDA MEMORY INC

发明人：KITANO TOMOHIRO;NAGAMINE HISASHI

分类号：G06F17/50;H01L21/82

主分类号：G06F17/50

摘要：PROBLEM TO BE SOLVED: To extract parasitic capacitance and parasitic resistance of a layout of a reduced process product without newly designing the layout data of the reduced process product. SOLUTION: In the extraction of a parasitic parameter of the reduced process product, the layout data of an existing product are prepared at first and the layout data are taken into a layout edition tool 55 (S101). Then, a mask region to be excluded from parasitic parameter extraction is specified (S102) for the layout data of the existing product. When the specification of the mask region is completed, wiring conversion processing is executed in response to a user's instruction (S103 to S108). In the processing, a wiring portion in an actual wiring layer present in the mask region is converted into a wiring portion in a virtual wiring layer. Then LPE processing for the converted layout is executed to extract the parasitic parameter of the whole layout or a specific part (S109). COPYRIGHT: (C)2008,JPO&INPIT