Multi port semiconductor memory device, has test mode control device executing core test by converting serial data communication into parallel data communication during selected core test mode, where control device has mode adjusting unit,申请号DE20061062024-传众专利搜索

Multi port semiconductor memory device, has test mode control device executing core test by converting serial data communication into parallel data communication during selected core test mode, where control device has mode adjusting unit

申请公布号：DE102006062024(A1)

申请号：DE20061062024

申请日期：2006.12.29

申请公布日期：2007.10.18

申请人：

HYNIX SEMICONDUCTOR INC.

发明人：DO, CHANG-HO

分类号：G11C29/48;G11C29/12

主分类号：G11C29/48

摘要：<p>The device has ports (PORT0-3) for execution of serial data communication with external devices by pads. A set of banks (BANK0-7) is provided for the execution of parallel data communication with the number of ports. A set of global data buses (GIOin, GIOout) supports/assists the parallel data communication between the ports and the banks. A test mode control device executes a core test by converting the serial data communication into the parallel data communication during a selected core test mode, where the mode control device has a mode adjusting unit (91).</p>