METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE,申请号US20070677478-传众专利搜索

METHOD FOR MANUFACTURING A WAFER LEVEL CHIP SCALE PACKAGE

申请公布号：US2007132108(A1)

申请号：US20070677478

申请日期：2007.02.21

申请公布日期：2007.06.14

申请人：

SAMSUNG ELECTRONICS CO., LTD.

发明人：LEE JIN-HYUK;KIM GU-SUNG;LEE DONG-HO;JANG DONG-HYEON

分类号：H01L23/48;H01L21/60;H01L23/31;H01L23/485

主分类号：H01L23/48

摘要：A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.