SYNCHRONOUS DETECTION CIRCUIT
申请公布号:JP2007019756(A)
申请号:JP20050197960
申请日期:2005.07.06
申请公布日期:2007.01.25
发明人:SAWADA KAZUNARI
分类号:H03D1/22
主分类号:H03D1/22
摘要:PROBLEM TO BE SOLVED: To provide a synchronous detection circuit or the like in which a circuit scale is small, there is no characteristic fluctuation, in-phase components are not detected from input signals and group delay is fixed. SOLUTION: A sample-and-hold circuit 14 samples and holds the input signals IN at the rise of a clock CLK from a waveform shaping circuit 11. That is, the sample-and-hold circuit 14 samples and holds the input signals IN when the rise of carriers S1 crosses zero. A sample-and-hold circuit 15 samples and holds inversion signals S3 from an inversion circuit 13 at the fall of the clock CLK. That is, the sample-and-hold circuit 15 samples and holds the inversion signals S3 when the fall of the carriers S1 crosses zero. An addition circuit 16 adds the output S5 of the sample-and-hold circuit 14 and the output S6 of the sample-and-hold circuit 15 and outputs the added result as detection signals OUT. COPYRIGHT: (C)2007,JPO&INPIT