Interleaved delay line for phase locked and delay locked loops
申请公布号:US7103791(B2)
申请号:US20050266552
申请日期:2005.11.03
申请公布日期:2006.09.05
分类号:G06F1/12;H03L7/06
主分类号:G06F1/12
摘要:An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
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