Damascene interconnect structure with cap layer

申请公布号：US2006118962(A1)

申请号：US20040004767

申请日期：2004.12.03

申请公布日期：2006.06.08

申请人：

HUANG JUI J;TSAI MINGHSING;SHUE SHAU-LIN;SU HUNG-WEN;KO TING-CHU

发明人：HUANG JUI J.;TSAI MINGHSING;SHUE SHAU-LIN;SU HUNG-WEN;KO TING-CHU

分类号：H01L23/48;H01L23/52

主分类号：H01L23/48

摘要：A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

RAW MATERIAL GAS FEED DEVICE

POSITION ADJUSTING DEVICE FOR SEAT AND THE LIKE OF VEHICLE