LAMINATED CHIP VARISTOR AND MANUFACTURING METHOD THEREOF,申请号JP20040173050-传众专利搜索

LAMINATED CHIP VARISTOR AND MANUFACTURING METHOD THEREOF

申请公布号：JP2005353844(A)

申请号：JP20040173050

申请日期：2004.06.10

申请公布日期：2005.12.22

申请人：

TDK CORP

发明人：MATSUOKA MASARU;MORIAI KATSUNARI;ABE TAKEHIKO;ISHII KOICHI

分类号：H01C7/10;(IPC1-7):H01C7/10

主分类号：H01C7/10

摘要：PROBLEM TO BE SOLVED: To provide a laminated chip varistor that appropriately maintains ESD withstand, while reducing the capacitance, and to provide a method for manufacturing the laminated chip varistor. SOLUTION: The laminated chip varistor 1 comprises a laminate 3, and a pair of external electrodes 5 formed in the laminate 3. The laminate 3 has a varistor 7, and a pair of external layers 9 arranged so that the varistor 7 is sandwiched. The varistor 7 includes a varistor layer 11 manifesting the varistor characteristics itself, and a pair of internal electrodes 13 arranged so that the varistor layer 11 is sandwiched. The pair of internal electrodes 13 are electrically connected to the external electrodes 5. A region overlapping with the pair of internal electrodes 13 in the varistor layer 11 has a region, made of a first element body that has ZnO as a main constituent and contains Co. The outer layer 9 has a region, made of a second element body that has ZnO as a main constituent, contains Co, and allows the content of Co to be smaller than that of the first element body. COPYRIGHT: (C)2006,JPO&NCIPI