Keyed clamp circuit

申请公布号：US2004165116(A1)

申请号：US20030736904

申请日期：2003.12.17

申请公布日期：2004.08.26

申请人：

SANYO ELECTRIC CO., LTD.

发明人：TAKIMOTO TAKAMASA

分类号：G09G5/00;H04N5/18;(IPC1-7):H04N5/53

主分类号：G09G5/00

摘要：The keyed clamp circuit of this invention has the clamp circuit for clamping the video signal including the equalizing pulse and the vertical synchronization signal based on the clamp pulse, the synchronization signal separation circuit for separating the synchronization signal from the video signal clamped by the clamp circuit, and the clamp pulse generation circuit for generating the clamp pulse based on the synchronization signal from the synchronization signal separation circuit. The clamp pulse for the equaling pulse with a pulse width, which is shorter during the equalizing pulse period compared to the pulse width during the vertical synchronization signal period, is generated. The clamp pulse can be generated based on the equalizing pulse and the vertical synchronization signal, performing the keyed clamping on the video signal even during the blanking pulse period.

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