PACKAGING METHOD FOR WAFER CLASS INTEGRATED CIRCUIT DEVICE,申请号JP20020004742-传众专利搜索

PACKAGING METHOD FOR WAFER CLASS INTEGRATED CIRCUIT DEVICE

申请公布号：JP2003218275(A)

申请号：JP20020004742

申请日期：2002.01.11

申请公布日期：2003.07.31

申请人：

FICTA TECHNOLOGY INC

发明人：CHIN SOKETSU

分类号：H01L23/12;H01L21/56;H01L21/60;(IPC1-7):H01L23/12

主分类号：H01L23/12

摘要：PROBLEM TO BE SOLVED: To provide the packaging method of a wafer class integrated circuit device capable of maintaining the perfectness of the wafer by providing a hold space to the thermal expansion of a buffer layer at the time of perfectly baking the buffer layer, by operating precut before perfectly hardening the buffer layer to reduce any stress to be imposed on the wafer at the time of thermally expanding the buffer layer. SOLUTION: A semiconductor wafer where a plurality of independently existing chip units are formed is provided and pre-cured, and the buffer layer is temporarily imperfectly baked so as to be imperfectly hardened, and the buffer layer is slightly put into a stable state. Then, cut edges are formed at the corresponding positions of each circuit layout unit boundary of the buffer layer, by operating precut so that a gap in which any buffer layer is not included can be arranged between the two adjacent circuit layout units. Then, the wafer is post-cured, the buffer layer is perfectly backed so as to be perfectly hardened, and the wafer is divided with the buffer into a plurality of independently operating circuit layout units so that an integrated circuit device can be configured. COPYRIGHT: (C)2003,JPO