Low cost bias technique for dual plate integrated capacitors,申请号US20020245022-传众专利搜索

Low cost bias technique for dual plate integrated capacitors

申请公布号：US6576977(B1)

申请号：US20020245022

申请日期：2002.09.17

申请公布日期：2003.06.10

申请人：

NATIONAL SEMICONDUCTOR CORPORATION

发明人：BEEMAN DONALD ST. JOHN;WERKING PAUL M.

分类号：H01L21/334;H01L27/07;(IPC1-7):H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119

主分类号：H01L21/334

摘要：An integrated dual-plate capacitor structure incorporates a small MOS transistor to reduce die area. The capacitor structure includes a semiconductor substrate having a first conductivity type and having a well region having a second conductivity type opposite the first conductivity type formed therein. An upper conductive plate and a lower conductive plate separated by a first layer of dielectric material are formed over the well region. The lower capacitor plate is separated from the upper surface of the well region by a second layer of dielectric material. A MOS transistor is formed in the semiconductor substrate. The MOS transistor includes space-apart source and drain regions of the second conductivity type that define a substrate channel region therebetween. A conductive gate is formed above the channel region and is separated therefrom by a layer of intervening dielectric material. The source region and the gate of the MOS transistor are connected to receive a bias voltage. The drain region of the MOS transistor is electrically connected to the well region. In an alternative embodiment, the drain of the MOS transistor is incorporated into the well region of the capacitor structure.