Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters,申请号US19990454681-传众专利搜索

Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters

申请公布号：US6496890(B1)

申请号：US19990454681

申请日期：1999.12.03

申请公布日期：2002.12.17

申请人：

AZEVEDO MICHAEL JOSEPH;BEARDSLEY BRENT CAMERON;OKBAY BITWODED;SPANEL CAROL;WALLS ANDREW DALE

发明人：AZEVEDO MICHAEL JOSEPH;BEARDSLEY BRENT CAMERON;OKBAY BITWODED;SPANEL CAROL;WALLS ANDREW DALE

分类号：G06F12/00;G06F13/00;G06F13/28;G06F13/40;(IPC1-7):G06F13/00

主分类号：G06F12/00

摘要：A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. Some of the masters are associated with the external bus and others are associated with the internal bus, and one of the bus masters is a control master associated with the internal processor. The scheme utilizes a shared bus hang prevention and recovery device having a circuitry and a control code. The circuitry is timing each pending request of the control master for the shared bus and initiating bus recovery if the shared bus is hung up, when the control master exceeded a pre-determined time period allowed for waiting to acquire the shared bus control and complete the transfer on the shared bus. The control code is used for monitoring and controlling the circuitry and terminating the transfer in progress causing the shared bus hang-up. During the bus recovery the circuitry prevents bus request grants to the master attached to the external bus until the master subsequent reset, and the control program instructions initiates transfers for all pending requests for the shared bus from the control master queue. Each transfer is being timed and terminated if the shared bus is hung up again. Upon the control master queue clearing, the internal processor executes the control program instructions to reset and reinitialize all masters and slaves on the shared bus.